Book Details

VLSI DESIGN

VLSI DESIGN

Published by uLektz

Course Code:PCEC4401

Author:uLektz

University: Biju Patnaik University of Technology (BPUT)

Regulation:2010

Categories:Electronics & Communication

Format : ico_bookePUB3 (DRM Protected)

Type :eBook

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Description :VLSI DESIGN of PCEC4401 covers the latest syllabus prescribed by Biju Patnaik University of Technology (BPUT) for regulation 2010. Author: uLektz, Published by uLektz Learning Solutions Private Limited.

Note : No printed book. Only ebook. Access eBook using uLektz apps for Android, iOS and Windows Desktop PC.

Topics
UNIT-I INTRODUCTION, FABRICATION OF MOSFET’S, MOS TRANSISTOR

1.1 Introduction: Historical Perspective, VLSI Design Methodologies, VLSI Design Flow, Design Hierarchy

1.2 Concept of Regularity, Modularity and Locality, VLSI Design Styles,Computer-Aided Design Technology

1.3 Fabrication of MOSFET’s:Introduction, Fabrication Processes Flow – Basic Concepts, The CMOS n-Well Process, Layout Design Rules, Stick Diagrams, Full-Customs Mask Layout Design

1.4 MOS Transistor:The Metal Oxide Semiconductor (MOS) Structure, The MOS System under External Bias

1.5 Structure and Operation of MOS Transistor (MOSFET), MOSFET Current-Voltage Characteristics, MOSFET Scaling and Small-Geometry Effects, MOSFET Capacitance

UNIT-II MOS INVERTERS, MOS INVERTERS – SWITCHING CHARACTERISTICS AND INTERCONNECT EFFECTS, COMBINATIONAL MOS LOGIC CIRCUITS

2.1 MOS Inverters–Static Characteristics: Introduction, Resistive-Load Inverters, Inverters with n-Type MOSFET Load, CMOS Inverter

2.2 MOS Inverters – Switching Characteristics and Interconnect Effects:Introduction, Delay-Time Definitions, Calculation of Delay-Times

2.3 Inverter Design with Delay Constraints, Estimation of Interconnect Parasitics, Calculation of Interconnect Delay, Switching Power Dissipation of CMOS Inverters

2.4 Combinational MOS Logic Circuits: Introduction, MOS Logic Circuits with Depletion nMOS Loads, CMOS Logic Circuits, Complex Logic Circuits, CMOS Transmission Gates (Pass Gates)

UNIT III SEQUENTIAL MOS LOGIC CIRCUITS, DYNAMIC LOGIC CIRCUITS, SEMICONDUCTOR MEMORIES, DESIGN FOR TESTABILITY

3.1 Sequential MOS Logic Circuits:Introduction, Behaviour of Bistable Elements, SR Latch Circuits, Clocked Latch and Flip-Flop Circuits, CMOS D-Latch and Edge-Triggered Flip-Flop

3.2 Dynamic Logic Circuits:Introduction, Basic Principles of Pass Transistor Circuits, Voltage Bootstrapping

3.3 Synchronous Dynamic Circuit Techniques, Dynamic CMOS Circuit Techniques, High Performance Dynamic CMOS Circuits

3.4 Semiconductor Memories: Introduction, Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), Non-volatile Memory, Flash Memory

3.5 Design for Testability: Introduction, Fault Types and Models, Ad Hoc Testable Design Techniques, Scan-Based Techniques, Built-In Self-Test (BIST) Techniques, Current Monitoring I DDQ Test

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