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Book Details

VLSI DESIGN

VLSI DESIGN

Published by uLektz

Course Code : RT41041
Author : uLektz
University : JNTU Kakinada
Regulation : 2013
Categories : Electronics & Communication
Format : ico_bookePUB3 (DRM Protected)
Type : eBook

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Description :VLSI DESIGN of RT41041 covers the latest syllabus prescribed by JNTU Kakinada for regulation 2013. Author: uLektz, Published by uLektz Learning Solutions Private Limited.

Note : No printed book. Only ebook. Access eBook using uLektz apps for Android, iOS and Windows Desktop PC.

Topics
UNIT-I: INTRODUCTION AND BASIC ELECTRICAL PROPERTIES OF MOS AND BI-CMOS CIRCUITS

1.1 Introduction: Introduction to IC Technology, MOS and related VLSI Technology, Basic MOS Transistors, Enhancement and Depletion modes of transistor action

1.2 IC production process, MOS and CMOS Fabrication processes, BiCMOS Technology, Comparison between CMOS and Bipolar technologies

1.3 Basic Electrical Properties Of MOS and Bi-CMOS Circuits: Ids versus Vds Relationships, Aspects of MOS transistor Threshold Voltage, MOS transistor Trans, Output Conductance and Figure of Merit

1.4 The Pass transistor, NMOS Inverter, Pull-up to Pull-down Ratio for NMOS inverter driven by another NMOS inverter, Alternative forms of pull-up

1.5 The CMOS Inverter, MOS transistor circuit model, Bi-CMOS Inverter, Latch-up in CMOS circuits and BiCMOS Latch-up Susceptibility

UNIT-II: MOS AND BI-CMOS CIRCUIT DESIGN PROCESSES

2.1 MOS Layers, Stick Diagrams

2.2 Design Rules and Layout, General observations on the Design rules, 2µ m Double Metal, Double Poly, CMOS/BiCMOS rules, 1.2µ m Double Metal, Double Poly CMOS rules

2.3 Layout Diagrams of NAND and NOR gates and CMOS inverter

2.4 Symbolic Diagrams-Translation to Mask Form

UNIT-III: BASIC CIRCUIT CONCEPTS AND SCALING OF MOS CIRCUITS

3.1 Basic Circuit Concepts: Sheet Resistance, Sheet Resistance concept applied to MOS transistors and Inverters, Area Capacitance of Layers, Standard unit of capacitance

3.2 The Delay Unit, Inverter Delays, Propagation Delays, Wiring Capacitances, Fan-in and fan-out characteristics

3.3 Choice of layers, Transistor switches

3.4 Realization of gates using NMOS, PMOS and CMOS technologies

3.5 Scaling Of MOS Circuits: Scaling models, Scaling factors for device parameters, Limits due to sub threshold currents, current density limits on logic levels and supply voltage due to noise

UNIT-IV: SUBSYSTEM DESIGN

4.1 Architectural issues, switch logic, Gate logic, examples of structured design

4.2 Clocked sequential circuits

4.3 System considerations, general considerations of subsystem design processes, an illustration of design processes

UNIT-V: VLSI DESIGN ISSUES

5.1 VLSI Design issues and design trends, design process, design for testability, technology options, power calculations, package selection

5.2 Clock mechanisms

5.3 Mixed signal design, ASIC design flow, FPGA design flow

5.4 Introduction to SoC design

UNIT-VI: FPGA DESIGN

6.1 Basic FPGA architecture, FPGA configuration, configuration modes

6.2 FPGA design process- FPGA design flow, FPGA families, FPGA design examples-stack, queue and shift register implementation using VHDL

6.3 Step-by-step approach of FPGA design process on Xilinx environment

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