# Digital Electronics

Course Code:EC6302

Author:uLektz

University:

Regulation:2013

Categories:Electronics & Communication

Format : ePUB3 (DRM Protected)

Type :eBook

Rs.199 Rs.30 Rs.85% off

Description :Digital Electronics of EC6302 covers the latest syllabus prescribed by Anna University, Tamil Nadu for regulation 2013. Author: uLektz, Published by uLektz Learning Solutions Private Limited.

Note : No printed book. Only ebook. Access eBook using uLektz apps for Android, iOS and Windows Desktop PC.

##### Topics
###### UNIT I MINIMIZATION TECHNIQUES AND LOGIC GATES

1.1 Minimization Techniques

1.2 Boolean postulates

1.3 De-Morgan"s Theorem

1.4 Principle of Duality

1.5 Boolean expression - Minimisation of Boolean expressions, MinTerm, Maxterm, Sum of products(SOP), Product of sums(POS)

1.6 Karnaugh map Minimization- Don‟t care conditions

1.7 Quine - Mc Cluskey method of minimization

1.8 Logic gates - AND,OR,NOT,NAND,NOR, Exclusive-OR & Exclusive-NOR

1.9 Implementations of Logic Functions using gates, NAND–NOR implementations - Multilevel gate implementations - Multi output gate implementations

1.10 TTL and CMOS Logic characteristics

1.11 Tristate gates

###### UNIT II COMBINATIONAL CIRCUITS

2.1 Design procedure – Half adder – Full Adder – Half subtractor – Full subtractor

2.2 Parallel binary adder and subtractor

2.6 Binary Multiplier and Divider

2.7 Multiplexer/ Demultiplexer

2.8 Decoder

2.9 Encoder

2.10 Parity checker and generator

2.11 Code converters

2.12 Magnitude Comparator

###### UNIT III SEQUENTIAL CIRCUITS

3.1 Latches, Flip-flops - SR, JK, D, T, and Master-Slave

3.2 Characteristic table and equation

3.3 Application table

3.4 Edge triggering and Level Triggering flip-flop

3.5 Realization of one flip flop using other flip flops

3.7 Asynchronous Ripple or serial counter and asynchronous Up/Down counter

3.8 Synchronous counters and Synchronous Up/Down counters

3.9 Programmable counters

3.10 Design of Synchronous counters - State diagram, State table, State minimization, State assignment, Excitation table and maps, Circuit implementation

3.11 Modulo–n counter

3.12 Registers – shift registers - Universal shift registers – Shift register counters – Ring counter – Shift counters

3.13 Sequence generators

###### UNIT IV MEMORY DEVICES

4.1 Memories Classification

4.2 ROM and ROM organization - PROM – EPROM – EEPROM –EAPROM

4.3 RAM and RAM organization – Write operation – Read operation – Memory cycle - Timing wave forms

4.4 Memory decoding and memory expansion

4.5 Static, Bipolar, MOSFET and Dynamic RAM cell

4.6 Programmable Logic Devices – Programmable Logic Array (PLA) -Programmable Array Logic (PAL) – Field Programmable Gate Arrays (FPGA)

4.7 Implementation of combinational logic circuits using ROM, PLA, PAL

###### UNIT V SYNCHRONOUS AND ASYNCHRONOUS SEQUENTIAL CIRCUITS

5.1 Synchronous Sequential Circuits - General Model, Classification – Design

5.2 Use of Algorithmic State Machine

5.3 Analysis of Synchronous Sequential Circuits

5.4 Asynchronous Sequential Circuits - Design of fundamental mode and pulse mode circuits

5.5 Incompletely specified State Machines

5.6 Problems in Asynchronous Circuits

5.7 Design of Hazard Free Switching circuits

5.8 Design of Combinational and Sequential circuits using VERILOG