Book Details

SWITCHING THEORY AND LOGIC DESIGN

SWITCHING THEORY AND LOGIC DESIGN

Published by uLektz

Course Code:13A04303

Author:uLektz

University: Jawaharlal Nehru Technological University, Anantapur (JNTUA)

Regulation:2013

Categories:Electronics & Communication

Format : ico_bookePUB3 (DRM Protected)

Type :eBook

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Description :SWITCHING THEORY AND LOGIC DESIGN of 13A04303 covers the latest syllabus prescribed by Jawaharlal Nehru Technological University, Anantapur (JNTUA) for regulation 2013. Author: uLektz, Published by uLektz Learning Solutions Private Limited.

Note : No printed book. Only ebook. Access eBook using uLektz apps for Android, iOS and Windows Desktop PC.

Topics
UNIT I : NUMBER SYSTEM & BOOLEAN ALGEBRA

1.1 Digital systems,Binary Numbers,Number base conversions,Complements of numbers,Signed binary numbers,Binary codes

1.2 Boolean Algebra-Basic definition,Basic theorems and properties ,Boolean Functions,Canonical & Standard forms,Other logic operations & Logic gates

UNIT II: GATE LEVEL MINIMIZATION

2.1 The map method,four variable, K-map.Five variable map,POS & SOP Simplification, Don’t care conditions

2.2 NAND & NOR Implementation,Other two level Implementation,Ex-or Function

2.3 Tabular Method- Simplification of Boolean function using tabulation Method

UNIT III: ANALYSIS AND SYNTHESIS OF COMBINATIONAL CIRCUITS

3.1 Combinational circuits, Analysis & Design procedure

3.2 Binary Adder-subtractor, Decimal Adder, Binary Multiplier, Magnitude comparator

3.3 Decoder, Encoders,Multiplexers

UNIT IV: ANALYSIS AND SYNTHESIS OF SEQUNTIAL CIRCUITS

4.1 Sequential Circuits,Latches Flips-Flops,Analysis of Clocked sequential circuits

4.2 State Reduction & Assignment,Design procedure,Registers & Counters Registers,Shift Registers

4.3 Ripple Counters,Synchronous counters, Other counters

UNIT V: Asynchronous sequential Logic & Programmable Memories

5.1 Introduction,Analysis Procedure,Circuits with Latches, Design Procedure,.Reduction of State flow tables ,Race-free State Assignment, Hazards

5.2 Random Access Memory, Memory Decoding Error detection and correction,ROM,PLA, PAL

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