# DIGITAL ELECTRONICS

Course Code:PET3I104

Author:uLektz

University:

Regulation:2016

Categories:Electronics & Communication

Format : ePUB3 (DRM Protected)

Type :eBook

Rs.199 Rs.30 Rs.85% off

Description :DIGITAL ELECTRONICS of PET3I104 covers the latest syllabus prescribed by Biju Patnaik University of Technology (BPUT) for regulation 2016. Author: uLektz, Published by uLektz Learning Solutions Private Limited.

Note : No printed book. Only ebook. Access eBook using uLektz apps for Android, iOS and Windows Desktop PC.

##### Topics
###### UNIT - I NUMBER SYSTEM, BOOLEAN ALGEBRA AND LOGIC GATES & COMBINATIONAL LOGIC DESIGN

1.1 Number System: Introduction to various number systems and their Conversion

1.2 Arithmetic Operation using 1’s and 2`s Compliments, Signed Binary and Floating Point Number Representation Introduction to Binary codes and their applications.

1.3 Boolean Algebra and Logic Gates: Boolean algebra and identities, Complete Logic set

1.4 Logic gates and truth tables, Universal logic gates, Algebraic Reduction and realization using logic gates

1.5 Combinational Logic Design: Specifying the Problem, Canonical Logic Forms, Extracting Canonical Forms, EX-OR Equivalence Operations, Logic Array

1.6 K-Maps: Two, Three and Four variable K-maps, NAND and NOR Logic Implementations.

###### UNIT - II LOGIC COMPONENTS, SYNCHRONOUS SEQUENTIAL LOGIC DESIGN AND BINARY COUNTERS

2.1 Logic Components: Concept of Digital Components, Binary Adders, Subtraction and Multiplication, An Equality Detector and comparator, Line Decoder, encoders, Multiplexers and De-multiplexers

2.2 Synchronous Sequential logic Design: sequential circuits

2.3 Storage elements: Latches (SR, D), Flip-Flops inclusion of Master-Slave, characteristics equation and state diagram of each FFs and Conversion of Flip-Flops

2.4 Analysis of Clocked Sequential circuits and Mealy and Moore Models of Finite State Machines

2.5 Binary Counters: Introduction, Principle and design of synchronous and asynchronous counters, Design of MOD-N counters, Ring counters, Decade counters, State Diagram of binary counters

###### UNIT - III SHIFT REGISTERS, MEMORY AND PROGRAMMABLE LOGIC, IC LOGIC FAMILIES AND BASIC HARDWARE DESCRIPTION LANGUAGE

3.1 Shift registers: Principle of 4-bit shift registers, Shifting principle, Timing Diagram, SISO, SIPO,PISO and PIPO registers

3.2 Memory and Programmable Logic: Types of Memories, Memory Decoding, error detection and correction, RAM and ROMs.

3.3 Programmable Logic Array, Programmable Array Logic, Sequential Programmable Devices

3.4 IC Logic Families: Properties - DTL, RTL, TTL, I2L and CMOS and its gate level implementation. A/D converters and D/A converters

3.5 Basic hardware description language: Introduction to Verilog/VHDL programming language, Verilog/VHDL program of logic gates, adders,Substractors, Multiplexers, Comparators, Decoders flip-flops, counters, Shift resistors.