Book Details

Switching Theory And Logic Design

Switching Theory And Logic Design

Published by uLektz

Course Code:RT22022

Author:uLektz

University: JNTU Kakinada

Regulation:2013

Categories:Electronics & Communication

Format : ico_bookePUB3 (DRM Protected)

Type :eBook

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Description :Switching Theory And Logic Design of RT22022 covers the latest syllabus prescribed by JNTU Kakinada for regulation 2013. Author: uLektz, Published by uLektz Learning Solutions Private Limited.

Note : No printed book. Only ebook. Access eBook using uLektz apps for Android, iOS and Windows Desktop PC.

Topics
UNIT – I REVIEW OF NUMBER OF SYSTEMS & CODES

1.1 Representation Of Numbers Of Different Radix, Conversation From One Radix To Another Radix, r-1’s Compliments And r’s Compliments Of Signed Members, Problem Solving

1.2 Bit Codes, BCD, Excess-3, 2421, 84-2-1 9’s Compliment Code Etc.,

1.3 Logic operations and error detection & correction codes; Basic logic operations -NOT, OR, AND, Universal building blocks, EX-OR, EX-NOR - Gates, Standard SOP and POS, Forms, Gray code, error detection, error correction codes (parity checking, even parity, odd parity, Hamming code)

1.4 Nand-Nand And Nor-Nor Realizations

UNIT – II MINIMIZATION TECHNIQUES

2.1 Boolean Theorems, Principle Of Complementation & Duality,Boolean theorems, principle of complementation & duality, De-morgan theorems, minimization of logic functions using Boolean theorems

2.2 Minimization Of Switching Functions Using k-Map Up To 6 Variables, Tabular Minimization, problem solving (code-converters using K-Map etc..)

UNIT – III COMBINATIONAL LOGIC CIRCUITS DESIGN

3.1 Design Of Half Adder, Full Adder, Half Subtractor, Full Subtractor, Applications Of Full Adders

3.2 4-Bit Binary Subtractor, Adder-Subtractor Circuit

3.3 Bcd Adder Circuit, Excess 3 Adder Circuit, Look-a-Head Adder Circuit

3.4 Design Of Decoder, Demultiplexer, 7 Segment Decoder ,Higher Order Demultiplexing, Encoder, Multiplexer, Higher Order Multiplexing, Realization Of Boolean Functions Using Decoders And Multiplexers,Priority Encoder

3.5 4-Bit Digital Comparator

UNIT – IV INTRODUCTION OF PLD’S

4.1 Prom, Pal, PLA-Basics Structures, Realization Of Boolean Function With PLDs, Programming Tables Of PLDs

4.2 Merits & Demerits Of Prom, PAL, PLA Comparison

4.3 Realization Of Boolean Functions Using Prom, PAL, PLA, programming Tables Of Prom, PAL, PLA

UNIT – V SEQUENTIAL CIRCUITS I

5.1 Classification Of Sequential Circuits (Synchronous And Asynchronous)

5.2 Basic Flip-Flops, Truth Tables And Excitation Tables (Nand Rs Latch, Nor Rs Latch, Rs Flip-Flop, Jk Flip-Flop, t Flip-Flop, d Flip-Flop With Reset And Clear Terminals)

5.3 Conversion From One Flip-Flop To Flip-Flop

5.4 Design Of Ripple Counters,Design Of Synchronous Counters, Johnson Counter, Ring Counter

5.5 Design Of Registers - Buffer Register, Control Buffer Register, Shift Register, Bi-Directional Shift Register, Universal Shift Register

UNIT – VI SEQUENTIAL CIRCUITS II

6.1 Finite State Machine; Analysis Of Clocked Sequential Circuits State Diagrams, State Tables, Reduction Of State Tables And State Assignment, Design Procedures

6.2 Realization Of Circuits Using Various Flip-Flops

6.3 Meelay To Moore Conversion And Vice-Versa

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