DIGITAL LOGIC DESIGN

 Course Code : RT21053 Author : uLektz University : JNTU Kakinada Regulation : 2013 Categories : Computer Science Format : ePUB3 (DRM Protected) Type : eBook

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Description :DIGITAL LOGIC DESIGN of RT21053 covers the latest syllabus prescribed by JNTU Kakinada for regulation 2013. Author: uLektz, Published by uLektz Learning Solutions Private Limited.

Note : No printed book. Only ebook. Access eBook using uLektz apps for Android, iOS and Windows Desktop PC.

Topics
Unit I: Number Systems

1.2 r’s Complement and (r-1)’s Complement Subtraction of Unsigned Numbers, Problems, Signed Binary Numbers

1.3 Weighted and Non weighted codes

Unit II: Logic Gates And Boolean Algebra

2.1 Basic Gates: NOT, AND, OR

2.2 Boolean Theorems, Complement And Dual of Logical Expressions

2.3 Universal Gates, Ex-Or and Ex-Nor Gates

2.4 SOP,POS

2.5 Minimizations of Logic Functions Using Boolean Theorems

2.6 Two level Realization of Logic Functions Using Universal Gates

2.7 Gate Level Minimization:Karnaugh Map Method (K-Map), Minimization of Boolean Functions maximum upto Four Variables, POS and SOP, Simplifications With Don’t Care Conditions Using K-Map

Unit III: Combinational Logic Circuits

3.2 Ripple Adders and Subtractors, Ripple Adder/Subtractor Using Ones and Twos Complement Method

3.3 Design of Decoders, Encoders

3.4 Multiplexers, Demultiplexers - Higher Order Demultiplexers and Multiplexers, Priority Encoder

3.5 Code Converters, Magnitude Comparator

Unit IV: Introduction to Sequential Logic Circuits

4.1 Classification of Sequential Circuits

4.2 Basic Sequential Logic Circuits, Latch and Flip-Flop, RS- Latch Using NAND and NOR Gates, Truth Tables

4.3 RS, JK, T and D Flip Flops -Truth and Excitation Tables

4.4 Conversion of Flip Flops, Flip Flops With Asynchronous Inputs (Preset and Clear)

Unit V: Registers and Counters

5.1 Design of Registers

5.2 Buffer Register, Control Buffer Registers, Bidirectional Shift Registers, Universal Shift Register

5.3 Design of Ripple Counters, Synchronous Counters and Variable Modulus Counters

5.4 Ring Counter Johnson Counter

Unit VI: Introduction to Programmable Logic Devices (PLOs)

6.1 PLA, PAL, PROM

6.2 Realization of Switching Functions Using PROM, PAL and PLA, Comparison of PLA, PAL and PROM