Book Details

DIGITAL ELECTRONICS CIRCUIT

DIGITAL ELECTRONICS CIRCUIT

Published by uLektz

Course Code:PCEC4202

Author:uLektz

University: Biju Patnaik University of Technology (BPUT)

Regulation:2010

Categories:Electronics & Communication

Format : ico_bookePUB3 (DRM Protected)

Type :eBook

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Description :DIGITAL ELECTRONICS CIRCUIT of PCEC4202 covers the latest syllabus prescribed by Biju Patnaik University of Technology (BPUT) for regulation 2010. Author: uLektz, Published by uLektz Learning Solutions Private Limited.

Note : No printed book. Only ebook. Access eBook using uLektz apps for Android, iOS and Windows Desktop PC.

Topics
UNIT – I NUMBER SYSTEM, BOOLEAN ALGEBRA AND LOGIC GATES & COMBINATIONAL LOGIC DESIGN

1.1 Number System: Introduction to Binary Numbers, Data Representation, Binary, Octal, Hexadecimal and Decimal Number System and their Conversion

1.2 Boolean Algebra and Logic Gates: Basic Logic Operation and Identities, Algebraic Laws, NOR and NAND Gates

1.3 Useful Boolean Identities, Algebraic Reduction, Complete Logic Sets, Arithmetic Operation using 1’s and 2`s Compliments, Signed Binary and Floating Point Number Representation

1.4 Combinational Logic Design: Specifying the Problem, Canonical Logic Forms, Extracting Canonical Forms, EX-OR Equivalence Operations, Logic Array

1.5 K-Maps: Two, Three and Four variable K-maps, NAND and NOR Logic Implementations

UNIT – II CONCEPTS IN VHDL, CMOS LOGIC CIRCUITS, C-MOS ELECTRONICS, MOSFETS, THE NOT FUNCTION IN C-MOS AND INTRODUCTION TO VLSI

2.1 Concepts in VHDL: Basic Concepts, Using a Hardware Description Language

2.2 Defining Module in VHDL, Structural and Combinational Modelling, Binary Words, Libraries, Learning VHDL

2.3 CMOS Logic Circuits: Voltages as Logic Variables

2.4 Logic Delay Times: Output Switching Times, Propagation Delay, Fan-In and Fan-out, Extension to other Logic Gate

2.5 C-MOS Electronics, MOSFETS, The NOT Function in C-MOS: Complimentary Pairs and the C-MOS Invertors

2.6 Logic Formation Using MOSFETS: the NAND and NOR Gate, C-MOS Logic Connection

2.7 Complex Logic Gates in C-MOS: 3-input Logic Gates, A general 4-input Logic Gate, Logic Cascades

2.8 Introduction to VLSI: Introduction, Lithography and Patterning

2.9 MOSFET Design Rules, Basic Circuit Layout, MOSFET Arrays and AOI Gates, Cells, Libraries, and Hierarchical Design, Floor Plans and Interconnect Wiring

UNIT – III LOGIC COMPONENTS, MEMORY ELEMENTS AND ARRAYS & SEQUENTIAL NETWORK

3.1 Logic Components: Concept of Digital Components, An Equality Detector, Line Decoder

3.2 Multiplexers and De-multiplexers

3.3 Binary Adders, Subtraction and Multiplication, Memory Elements and Arrays: General Properties

3.4 Latches, Clock and Synchronization

3.5 Master-Slave and Edge-triggered Flip-flops, Registers

3.6 RAM and ROM’s, C-MOS Memories

3.7 Sequential Network: Concepts of Sequential Networks

3.8 Analysis of Sequential Networks: Single State and Multivariable Networks, Sequential Network Design

3.9 Binary Counters

3.10 Importance of state machine

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